1. Field of the Invention
The present invention relates to a logic circuit and semiconductor integrated circuit device, and more particularly to technology effective for use in a Non Threshold Logic (NTL) circuit, a Super Push-pull Logic (SPL) circuit and further high-speed logical integrated circuits using these logic circuits as a basic circuit, for example.
2. Description of the Prior Art
The NTL circuit is proposed as a high-speed and low electric power consuming digital logical circuit. For example, a SPL circuit and the like in which an Active Pull-Down (APD) circuit is provided in said NTL circuit are disclosed in Japanese Unexamined Provisional Publication, No. 3-64123 (prior art 1). Further, in order to enhance the collector response of the SPL circuit, a SPL-B circuit is also proposed in Japanese Unexamined Provisional Publication, No. 3-267817 (prior art 2).
FIG. 1 is a circuit diagram showing one example of the conventional SPL circuit (prior art 1). As shown in FIG. 1, the conventional SPL circuit has a phase splitting circuit comprising a bipolar transistor Q21 and resistive elements R21 and R23 which are connected in series between a positive power supply terminal 1 and a negative power supply terminal 2. An input signal VIN is input into a base of the transistor Q21. In between the positive power supply terminal 1 and the negative power supply terminal 2, a bipolar transistor Q23 and a resistive element R24 are connected in series, and a negative power supply terminal 3 is connected to a base of the transistor Q23. A capacitor C22 is connected between a node A2 connecting the transistor Q21 and the resistive element R23 and a node A3 connecting the transistor Q23 and the resistive element R24. Further, a bipolar transistor Q22 and a bipolar transistor Q24 are connected in series between the positive power supply terminal 1 and the negative power supply terminal 2, a base of the transistor Q22 is connected to a node A1 and a base of the transistor Q24 is connected to the node A3. Both an emitter of the transistor Q22 and a collector of the transistor Q24 are connected to an output terminal VOUT.
There exists a stray capacitance CC3 between the collector node (Node A1) of this phase splitting circuit and the negative power supply terminal 2. In this case, when the level of an input signal VIN is high, the transistor Q21 is turned on so that the stray capacitance CC3 in the collector node (Node A1) is quickly discharged through the transistor Q21.
When the level of the input signal VIN is low, however, the stray capacitance CC3 of the collector node (Node A1) is passively charged through the resistive element R21 because the transistor Q21 is at the off-state. Therefore, the raising of the potential at the collector node (Node A1) becomes slow according to the time constant determined by the product of a value of the resistive element R21 and the stray capacitance CC3, and there was a problem therefore that the propagation delay time responding to the low level change of the input signal VIN becomes longer.
As one of the approaches to overcome such a problem, the SPL-B circuit is proposed. FIG. 2 is a circuit diagram showing the constitution of the SPL-B circuit (prior art 2). In FIG. 2, the same numeral is used for the elements or parts which have the same function as those shown in FIG. 1 and a detailed explanation will be omitted. As shown in FIG. 2, the conventional SPL-B circuit is a circuit in which a P-channel MOSFET Q5 is connected in parallel with a resistive element R21 in a phase splitting circuit area comprising a transistor Q21 and resistive elements R21 and R23 in the SPL circuit. To a gate of this MOSFET Q5, the input terminal VIN is connected.
In this SPL-B circuit, the stray capacitance CC2 of the collector node (node A1) is actively and quickly charged through the P-channel MOS transistor Q5 because the transistor Q5 is turned on when the level of the input signal VIN is low. On the other hand, when the level of the input signal VIN is high, the P-channel MOSFET Q5 is in an off-state and therefore does not prevent a quick discharge of the collector node (node A1) through the transistor Q21 in the phase splitting circuit area.
This improved SPL-B circuit was aimed to charge the collector node at high-speed. The MOS transistor, however, generally has a low ability of the current drive. Furthermore, there was another problem in the SPL-B circuit that the assembly process obviously becomes comprehensive because the assembly process for the MOS transistor is needed in addition to the assembly process for a bipolar transistor since the MOS transistor must be combined into the SPL circuit comprising the bipolar transistor.
Another problem in this circuit is that the input capacity against the input signal is increased by the input capacity of the P-channel MOSFET Q5 so that the propagation delay time becomes longer because switching of the P-channel MOSEFT Q5 is made by the input signal VIN.